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RT9724 ? ds9724-02 july 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ordering information 100m , 2a slew rate controlled load switch general description the RT9724 is a cost-effective, low-voltage, single n-mosfet high-side power switch ic. low switch-on resistance (typ. 100m ) and low supply current (typ. 50ua) are realized in this ic. the RT9724 integrates an over- current protection circuit, a short fold back circuit, a thermal shutdown circuit and an under-voltage lockout circuit for overall protection. besides, a slew rate controlled function is embedded for turn-on rising time control. the RT9724 is available in sot-23-5 and wdfn- 8l 2x2 package. features z z z z z 100m (typ.) n-mosfet switch z z z z z operating range : 2.7v to 5.5v z z z z z reverse blocking current z z z z z under voltage lockout z z z z z thermal protection with foldback z z z z z over current protection z z z z z short circuit protection z z z z z slew rate limited turn-on time 3ms (5v) z z z z z rohs compliant and halogen free applications z cellular phones z digital still camera z hot swap supplies z notebook computers z personal communication devices z personal digital assistants marking information pin configurations (top view) wdfn-8l 2x2 sot-23-5 nc vout vin vin vin en gnd 7 6 5 1 2 3 4 8 gnd 9 vin en gnd vout vin vin 4 23 5 RT9724 package type b : sot-23-5 qw : wdfn-8l 2x2 (w-type) lead plating system g : green (halogen free and pb free) note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. 1y=dnn 1y= : product code dnn : date code gvw gv : product code w : date code RT9724gb RT9724gqw
RT9724 2 ds9724-02 july 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram functional pin description pin no. sot-23-5 wd fn-8l 2x2 pin name pin function 1 3 en chip enable (active high). 2 4, 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 3 2 vout power-switch output. 4, 5 5, 6, 7, 8 vin power input voltage. -- 1 nc no internal connection. gate control output voltage detection oscillator uvlo charge pump bias thermal protection current limiting vout vin gnd en auto discharge typical application circuit vout vin gnd RT9724 2.7v to 5.5v en chip enable load c out 0.1f 1f c in
RT9724 3 ds9724-02 july 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics (v in = 5v, c in = 1 f, c out = 0.1 f, t a = 25 c, unless otherwise specified) recommended operating conditions (note 4) z supply voltage, vin ------------------------------------------------------------------------------------------------------ 2.7v t o 5.5v z enable input voltage, en ------------------------------------------------------------------------------------------------ 0v to 5.5v z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 100 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply voltage, vin ------------------------------------------------------------------------------------------------------ 6v z enable input voltage, en ------------------------------------------------------------------------------------------------ ? 0.3v to 6v z power dissipation, p d @ t a = 25 c sot-23-5 -------------------------------------------------------------------------------------------------------------------- 0.458w wdfn-8l 2x2 -------------------------------------------------------------------------------------------------------------- 0.833w z package thermal resistance (note 2) sot-23-5, ja -------------------------------------------------------------------------------------------------------------- 218.1 c/w wdfn-8l 2x2, ja -------------------------------------------------------------------------------------------------------- 120 c/w z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c z esd susceptibility (note 3) hbm (human body model) ---------------------------------------------------------------------------------------------- 4kv parameter symbol test conditions min typ max unit operation voltage v in 2.7 -- 5 v under voltage lookout v uvlo v in falling 1.3 1.7 2.1 v under voltage lockout hysteresis v uvlo -- 50 -- mv quiescent current i q en = high -- 50 70 a off supply current i shdn en = low, v out = open -- -- 1 a off switch current i leakage en = low, v out = 0 -- -- 1 a on-resistance r ds(on) v in = 3.3v, i out = 1.3 a -- 100 120 m current limiting i lim v in = 3.3v, v out = 2.3v 1.5 2 2.5 a short circuit current i sc_fb v out = 0v, measured prior to thermal shutdown 0.4 0.8 1.5 a v out > 1v -- 130 -- c thermal shutdown threshold t sd v out = 0v -- 100 -- c hysteresis -- 20 -- c logic-low v il v in = 2.7v to 5.5v -- -- 0.8 v en threshold voltage logic-high v ih v in = 2.7v to 5.5v 2 -- -- v enable input leakage i en v en = 5.5v -- -- 1 a
RT9724 4 ds9724-02 july 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit output turn-on delay time t d_on v in = 5v, r load = 10 -- 60 100 s output turn-on rise time t on v in = 5v, r load = 10 1 3 -- ms output turn-off delay time t d_off v in = 5v, r load = 10 -- 4 10 s output pull-down resistance during off r discha rge en = low -- 150 -- note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT9724 5 ds9724-02 july 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics shutdown current vs. temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -40-20 0 20406080100 temperature (c) shutdown current (a) 1 v in = 5.5v, v en = 0v, no load shutdown current vs. input voltage 0.00 0.05 0.10 0.15 0.20 0.25 0.30 2.7 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) shutdown current (a) 1 v en = 0v,no load quiescent current vs. temperature 20 22 24 26 28 30 -40 -20 0 20 40 60 80 100 temperature (c) quiescent current (a ) v in = v en = 5.5v, no load quiescent current vs. input voltage 15 18 21 24 27 30 2.7 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) quiescent current (a ) v en = 5v, no load on resistance vs. temperature 80 90 100 110 120 130 140 150 -40 -20 0 20 40 60 80 100 temperature (c) on resistance (m ? ) v in = v en = 5v, i out = 1.5a on resistance vs. input voltage 110 111 112 113 114 115 2.7 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) on resistance (m ? ) en = 5v, i out = 1.5a
RT9724 6 ds9724-02 july 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. current limit vs. temperature 1.5 1.6 1.7 1.8 1.9 2 -40 -20 0 20 40 60 80 100 temperature (c) current limit (a) v en = 5v short current vs. temperature 0.7 0.8 0.9 1 1.1 1.2 -40-20 0 20406080100 temperature (c) short current (a) v in = v en = 5v short current vs. input voltage 0.7 0.8 0.9 1 1.1 1.2 2.7 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) short current (a) v en = 5v output voltage vs. output current 0 1 2 3 4 5 6 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 output current (a) output voltage (v) v in = 3.3v v in = 5.5v v en = 5v uvlo threshold vs. temperature 1.1 1.3 1.5 1.7 1.9 2.1 -40-20 0 20406080100 temperature (c) uvlo threshold (v) rising falling v en = 5v current limit vs. input voltage 1.5 1.6 1.7 1.8 1.9 2 2.7 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) current limit (a) v en = 5v
RT9724 7 ds9724-02 july 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. turn-off delay time vs. input voltage 0.2 0.4 0.6 0.8 1 1.2 2.7 3.1 3.4 3.7 4 4.3 4.6 5 5.2 5.5 input voltage (v) turn-off delay time (s) v en = 5v, r load = 10 power on from en v out (2v/div) v en (5v/div) i out (1v/div) time (2.5ms/div) v in = v en = 5.5v, r load = 3 power on from v in v in (2v/div) v out (2v/div) time (5ms/div) v in = v en = 5v, no load turn-on rising time vs. input voltage 2.5 2.8 3.1 3.4 3.7 4 2.7 3.1 3.4 3.7 4 4.3 4.6 5 5.2 5.5 input voltage (v) turn-on rising time (ms ) v en = 5v, r load = 10 turn on rising time vs. temperature 3 3.4 3.8 4.2 4.6 5 -40 -20 0 20 40 60 80 100 temperature ( c) turn on rising time (ms) v in = v en = 5v, r load = 10 turn off delay time vs. temperature 0.2 0.3 0.4 0.5 0.6 -40-200 20406080100 temperature (c) turn off delay time (s) v en = 5v, r load = 10
RT9724 8 ds9724-02 july 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. universal serial bus (usb) & power distribution the goal of usb is to enable device from different vendors to interoperate in an open architecture. usb features include ease of use for the end user, a wide range of workloads and applications, robustness, synergy with the pc industry, and low-cost implementation. benefits include self-identifying peripherals, dynamically attachable and reconfigurable peripherals, multiple connections (support for concurrent operation of many devices), support for as many as 127 physical devices, and compatibility with pc plug-and-play architecture. the universal serial bus connects usb devices with a usb host: each usb system has one usb host. usb devices are classified either as hubs, which provide additional attachment points to the usb, or as functions, which provide capabilities to the system (for example, a digital joystick). hub devices are then classified as either bus-power hubs or self-powered hubs. a bus-powered hub draws all of the power to any internal functions and downstream ports from the usb connector power pins. the hub may draw up to 500ma from the upstream device. external ports in a bus-powered hub can supply up to 100ma per port, with a maximum of four external ports. applications information the RT9724 is a single n-mosfet high-side power switches with enable input, optimized for self-powered and bus-powered universal serial bus (usb) applications. the RT9724 is equipped with a charge pump circuitry to drive the internal n-mosfet switch; the switch's low r ds(on) , 100m , meets usb voltage drop requirements. input and output v in (input) is the power source connection to the internal circuitry and the drain of the mosfet. v out (output) is the source of the mosfet. in a typical application, current flows through the switch from v in to v out toward the load. if v out is greater than v in , current will flow from v out to v in since the mosfet is bidirectional when on. unlike a normal mosfet, there is no parasitic body diode between drain and source of the mosfet, the RT9724 prevents reverse current flow if v out is externally forced to a higher voltage than v in when the chip is disabled (v en < 0.8v). chip enable input the switch will be disabled when the en pin is in a logic low condition. during this condition, the internal circuitry and mosfet will be turned off, reducing the supply current to 0.1 a typical. floating the en may cause unpredictable operation. en should not be allowed to go negative with respect to gnd. the en pin may be directly tied to v in to keep the part on. soft start for hot plug-in applications in order to eliminate the upstream voltage droop caused by the large inrush current during hot-plug events, the ? soft-start ? feature effectively isolates the power source from extremely large capacitive loads, satisfying the usb voltage droop requirements. under voltage lockout under voltage lockout (uvlo) prevents the mosfet switch from turning on until the input voltage exceeds approximately 1.75v. if input voltage drops below approximately 1.7v, uvlo turns off the mosfet switch. under-voltage detection functions only when the switch is enabled. current limiting and short-circuit protection the current limit circuitry prevents damage to the mosfet switch and the hub downstream port but can deliver load current up to the current limit threshold of typically 2a. when a heavy load or short circuit is applied to an enabled switch, a large transient current may flow until the current limit circuitry responds. once this current limit threshold is exceeded, the device enters constant current mode until the thermal shutdown occurs or the fault is removed. d g s d g s normal mosfet RT9724
RT9724 9 ds9724-02 july 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. supply filter/bypass capacitor a 1uf low-esr ceramic capacitor from v in to gnd, located at the device is strongly recommended to prevent the input voltage drooping during hot-plug events. however, higher capacitor values will further reduce the voltage droop on the input. furthermore, without the bypass capacitor, an output short may cause sufficient ringing on the input (from source lead inductance) to destroy the internal control circuitry. the input transient must not exceed 6v of the absolute maximum supply voltage even for a short duration. output filter capacitor a low-esr 150uf aluminum electrolytic or tantalum between v out and gnd is strongly recommended to meet the 330mv maximum droop requirement in the hub v bus (per usb 2.0, output ports must have a minimum 120 f of low-esr bulk capacitance per hub). standard bypass methods should be used to minimize inductance and self-powered hub power for the internal functions and downstream ports does not come from the usb, although the usb interface may draw up to 100ma from its upstream connection, to allow the interface to function when the remainder of the hub is powered down. the hub must be able to supply up to 500ma on all of its external downstream ports. please refer to universal serial specification revision 2.0 for more details on designing compliant usb hub and host systems. over current protection devices such as fuses and ptc resistors (also called polyfuse or polyswitch) have slow trip times, high on-resistance, and lack the necessary circuitry for usb-required fault reporting. the faster trip time of the RT9724 power distribution allows designers to design hubs that can operate through faults. the RT9724 provides low on-resistance and internal fault- reporting circuitry to meet voltage regulation and fault notification requirements. because the devices are also power switches, the designer of self-powered hubs has the flexibility to turn off power to output ports. unlike a normal mosfet, the devices have controlled rise and fall times to provide the needed inrush current limiting required for the bus-powered hub power switch. resistance between the bypass capacitor and the downstream connector to reduce emi and decouple voltage droop caused when downstream cables are hot-insertion transients. ferrite beads in series with v bus , the ground line and the 0.1 f bypass capacitors at the power connector pins are recommended for emi and esd protection. the bypass capacitor itself should have a low dissipation factor to allow decoupling at higher frequencies. voltage drop the usb specification states a minimum port-output voltage in two locations on the bus, 4.75v out of a self- powered hub port and 4.4v out of a bus-powered hub port. as with the self-powered hub, all resistive voltage drops for the bus-powered hub must be accounted for to guarantee voltage regulation (see figure 7-47 of universal serial specification revision 2.0 ). the following calculation determines v out (min) for multi- ple ports (n ports ) ganged together through one switch (if using one switch per port, n ports is equal to 1) : v out (min) = 4.75v ? [ i i x ( 4 x r conn + 2 x r cable ) ] ? (0.1a x n ports x r switch ) ? v pcb where r conn = resistance of connector contacts (two contacts per connector) r cable = resistance of upstream cable wires (one 5v and one gnd) r switch = resistance of power switch (90m typical for rt9715) v pcb = pcb voltage drop the usb specification defines the maximum resistance per contact ( r conn ) of the usb connector to be 30m and the drop across the pcb and switch to be 100mv. this basically leaves two variables in the equation: the resistance of the switch and the resistance of the cable. if the hub consumes the maximum current (i i ) of 500ma, the maximum resistance of the cable is 90m .
RT9724 10 ds9724-02 july 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. the resistance of the switch is defined as follows : r switch = { 4.75v ? 4.4v ? [ 0.5a x ( 4 x 30m + 2 x 90m ) ] ? v pcb } ( 0.1a x n ports ) = (200mv ? v pcb ) ( 0.1a x n ports ) if the voltage drop across the pcb is limited to 100mv, the maximum resistance for the switch is 250m for four ports ganged together. the RT9724, with its maximum 100m on-resistance over temperature, can fit the demand of this requirement. thermal shutdown thermal protection limits the power dissipation in the RT9724. when the operation junction temperature exceeds 130 c, the otp circuit starts the thermal shutdown function and turns the pass element off. the pass element turn on again after the junction temperature cools to 80 c. the RT9724 lowers its otp trip level from 130 c to 100 c when output short circuit occurs (v out < 1v) as shown in figure 1. figure 1. short circuit thermal folded back protection when output short circuit occurs (patent) v out short to gnd 1v v out i out thermal shutdown otp trip point 130 c 110 c 100 c 80 c ic temperature thermal considerations the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating conditions specification, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ja is layout dependent. for sot-23-5 package, the thermal resistance ja is 218.1 c/w on the standard jedec 51-7 four layers thermal test board. for wdfn-8l 2x2 package, the thermal resistance ja is 120 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (218.1 c/w) = 0.458w for sot-23-5 package p d(max) = (125 c ? 25 c) / (120 c/w) = 0.833w for wdfn-8l 2x2 package the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . the figure 2 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. figure 2. derating curve of maximum power dissipation 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0255075100125 ambient temperature (c) maximum power dissipation (w ) wdfn-8l 2x2 sot-23-5 single layer pcb
RT9724 11 ds9724-02 july 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout consideration for best performance of the RT9724.the following guidelines must be followed : ` input and output capacitors should be placed close to the ic and connected to ground plane to reduce noise coupling. ` the gnd shoule be connected to a strong ground plane for heat sink. ` keep the main current traces as possible as short and wide. nc vout vin vin vin en 7 6 5 1 2 3 4 8 gnd vin g n d 9 c out c in the input and output capacitor should be placed as close as possible to the ic. the main current trace should be as possible as short and wide. figure 4. pcb layout for wdfn package en gnd vout vin vin 4 23 5 c out c in the input and output capacitor should be placed as close as possible to the ic. the main current trace should be as possible as short and wide. figure 3. pcb layout guide for sot-23-5 package
RT9724 12 ds9724-02 july 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. a a1 e b b d c h l dimensions in millimeters dimensions in inches symbol min max min max a 0.889 1.295 0.035 0.051 a1 0.000 0.152 0.000 0.006 b 1.397 1.803 0.055 0.071 b 0.356 0.559 0.014 0.022 c 2.591 2.997 0.102 0.118 d 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 h 0.080 0.254 0.003 0.010 l 0.300 0.610 0.012 0.024 sot-23-5 surface mount package outline dimension
RT9724 13 ds9724-02 july 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. w-type 8l dfn 2x2 package dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 1.950 2.050 0.077 0.081 d2 1.000 1.250 0.039 0.049 e 1.950 2.050 0.077 0.081 e2 0.400 0.650 0.016 0.026 e 0.500 0.020 l 0.300 0.400 0.012 0.016 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a

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